The present invention relates in general to digital data processing circuits and in particular to a method and circuit for generating an output floating point number approximately equal to the inverse of an input floating point number.
In digital computers, floating point numbers are usually characterized by a set of bits representing a mantissa, another set of bits representing an exponent, and a single bit representing the sign (positive or negative) of the number. Floating point processors often include high speed circuits for adding, subtracting, and multiplying binary floating point numbers, and a circuit for finding the reciprocal of a binary floating point number. Division of one number by another is typically carried out by first inverting the denominator and then multiplying the inverse of the denominator by the numerator. But circuits for inverting numbers have either been slow or expensive, or produce output numbers that approximate an inverse with relatively low accuracy. One typical circuit, illustrated in FIG. 1, generates an output number approximating the inverse (1/D) of an input floating point number D. The circuit of FIG. 1 utilizes a lookup table 10, suitably implemented by a read only memory (ROM) addressed by the mantissa of input floating point number D, to produce the mantissa of the inverse number 1/D. Another lookup table 12, suitably implemented by another ROM addressed by the exponent of the input floating point number, negates and offsets the input number exponent to produce the exponent of the output number. The output number is then formed by concatenating the mantissa and exponent outputs of tables 10 and 12 and the sign bit of D. The circuit of FIG. 1 inverts numbers quickly because it requires only two ROM accesses that can be carried out simultaneously. However, the circuit is impractical for inverting floating point numbers with high accuracy due to the size of the ROM needed to implement table 10. For example, when the input and output numbers have 23-bit mantissas, a ROM implementing table 10 would have to store over eight million separately addressable 23-bit numbers.
FIG. 2 shows a well-known circuit of the prior art for implementing the following inversion algorithm: EQU Rb=Ra*[2-(Ra*D)]
where Ra is a "first pass" estimate of the inverse (1/D) of an input floating point number D, and Rb is a "second pass" estimate of 1/D. The "*" symbol represents multiplication. Ra is produced by a circuit similar to the circuit of FIG. 1 including mantissa and exponent lookup tables 10' and 12', similar to tables 10 and 12 of FIG. 1 except that the mantissa lookup table 10' is addressed only by a most significant portion of the bits of the mantissa of input number D. For example, when the mantissa of D is 23 bits, only the most significant 12 bits of D need be applied to address a ROM implementing table 10. The ROM would store only 4096 separately addressable 12-bit data words, and a ROM of such size is inexpensive and readily available. The first pass estimate output Ra and the input number D are multiplied by a floating point multiplier 14, and the result is subtracted from the constant 2 by a floating point subtractor 16 to provide a floating point number equal to 2-(Ra*D). The output of subtractor 16 is then multiplied by another multiplier 18 to produce the second pass estimate Rb of the inverse of (1/D) which has a mantissa accurate to about 23 bits. While the circuit of FIG. 2 utilizes a substantially smaller ROM in comparison to the circuit of FIG. 1 to provide an output estimate of 1/D of similar accuracy, the circuit of FIG. 2 requires more time to invert a number, because in addition to performing a ROM access, it must also subsequently perform two floating point multiplications and a floating point subtraction.